upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 369

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

16-bit Timer/Event Counter P (TMP)
TPnIOC0
TPnIOC2
0
Note
0
0
(c) TMPn I/O control register 0 (TPnIOC0)
(d) TMPn I/O control register 2 (TPnIOC2)
(e) TMPn counter read buffer register (TPnCNT)
(f) TMPn capture/compare register 0 (TPnCCR0)
(g) TMPn capture/compare register 1 (TPnCCR1)
TMPn I/O control register 1 (TPnIOC1) and TMPn option register 0 (TPnOPT0)
are not used in the external event count mode.
Preliminary User’s Manual U17566EE1V2UM00
0
The count value of the 16-bit counter can be read by reading the TPnCNT
register.
If D
match interrupt request signal (INTTPnCC0) is generated when the
number of external event counts reaches (D
Usually, the TPnCCR1 register is not used in the external event count
mode. However, the set value of the TPnCCR1 register is transferred to the
CCR1 buffer register. When the count value of the 16-bit counter matches
the value of the CCR1 buffer register, a compare match interrupt request
signal (INTTPnCC1) is generated.
Therefore, mask the interrupt signal by using the interrupt mask flag
(TPnCCMK1).
0
0
is set to the TPnCCR0 register, the counter is cleared and a compare
0
0
0
TPnOL1
0/1
TPnEES1
0/1
TPnOE1 TPnOL0
0/1
TPnEES0 TPnETS1 TPnETS0
0/1
0
0
TPnOE0
0
0
+ 1).
0: Disable TOPn0 pin output
0: Disable TOPn1 pin output
1: Enable TOPn1 pin output
Setting of output level with
operation of TOPn1 pin
disabled
0: Low level
1: High level
0
Select valid edge
of external event
count input
Chapter 11
369