upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 684

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 19
684
CCERC
VALID
AL
0
1
0
1
0
1
Error counter clear bit
The CnERC and CnINFO registers are not cleared in the initialization mode.
The CnERC and CnINFO registers are cleared in the initialization mode.
Bit to set operation in case of arbitration loss
Re-transmission is not executed in case of an arbitration loss in the single-shot mode.
Re-transmission is executed in case of an arbitration loss in the single-shot mode.
Valid receive message frame detection bit
A valid message frame has not been received since the VALID bit was last cleared to 0.
A valid message frame has been received since the VALID bit was last cleared to 0.
Note
Note
Note
1.
2.
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4.
1.
2.
1.
2.
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5.
Preliminary User’s Manual U17566EE1V2UM00
PSMODE1
The CCERC bit is used to clear the CnERC and CnINFO registers for re-
initialization or forced recovery from the bus-off status. This bit can be set
to 1 only in the initialization mode.
When the CnERC and CnINFO registers have been cleared, the CCERC
bit is also cleared to 0 automatically.
The CCERC bit can be set to 1 at the same time as a request to change
the initialization mode to an operation mode is made.
The CCERC bit is read-only in the CAN sleep mode or CAN stop mode.
The AL bit is valid only in the single-shot mode.
The AL bit is read-only in the CAN sleep mode or CAN stop mode.
Detection of a valid receive message frame is not dependent upon storage
in the receive message buffer (data frame) or transmit message buffer
(remote frame).
Clear the VALID bit (0) before changing the initialization mode to an
operation mode.
If only two CAN nodes are connected to the CAN bus with one transmitting
a message frame in the normal mode and the other in the reception mode,
the VALID bit is not set to 1 before the transmitting node enters the error
passive status.
The VALID bit is read-only in the CAN sleep mode or CAN stop mode.
To clear the VALID bit, set the Clear VALID bit to 1 first and confirm that the
VALID bit is cleared. If it is not cleared, perform clearing processing again.
0
0
1
1
PSMODE0
0
1
0
1
Power save mode
No power save mode is selected.
CAN sleep mode
Setting prohibited
CAN stop mode
CAN Controller (CAN)