upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 813
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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LCD Controller/Driver (LCD-C/D)
Bit Position
3 to 2
1 to 0
Initial Value
Table 22-4
Address
Caution
Access
LCDC0[3:2]
LCDC0[1:0]
Bit Name
Note
(1)
LCDC0 - LCD clock control register
The 8-bit LCDC0 register determines the duty cycle frequency f
This register can be read/written in 8-bit or 1-bit units.
FFFF FB00
00
LCDC0 register contents
1.
2.
The frequency of LCDCLK is determined in the Clock Generator.
The root clock for LCDCLK can be selected from the main, sub, or ring
oscillator. It can be identical with the clock source or it can be a fraction thereof.
Preliminary User’s Manual U17566EE1V2UM00
H
Bit 4 must always be 0.
Changing the root clock source for LCDLCK will also change the Watch
Timer clock WTCLK. For details refer to the “Clock Generator“ on page 129.
. This register is cleared by any reset.
R
7
0
Function
Selects the LCD clock
Selects the duty cycle frequency
LCDC03
LCDC01
0
0
1
1
0
0
1
1
H
R
6
0
LCDC02
LCDC00
0
1
0
1
0
1
0
1
R
5
0
Selected LCD clock (f
LCDCLK
SPCLK7
SPCLK9
reserved
Selected duty cycle frequency (f
LCD clock divided by 2
LCD clock divided by 2
LCD clock divided by 2
LCD clock divided by 2
R/W
4
0
LCDC03 LCDC02 LCDC01 LCDC00
R/W
3
6
7
8
9
LCD0
R/W
)
2
LCD1
R/W
)
1
LCD1
Chapter 22
.
R/W
0
813
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