upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 622

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 18
622
Transfer lines
Master 1
Master 2
Figure 18-13
SDAn
SDAn
SDAn
SCLn
SCLn
SCLn
18.12 Arbitration
When several master devices simultaneously output a start condition (when
the IICCn.STTn bit is set to 1 before the IICSn.STDn bit is set to 1),
communication between the master devices is performed while the number of
clocks is adjusted until the data differs. This kind of operation is called
arbitration.
When one of the master devices loses in arbitration, an arbitration loss flag
(IICSn.ALDn bit) is set to 1 via the timing by which the arbitration loss
occurred, and the SCLn and SDAn lines are both set to high impedance, which
releases the bus.
Arbitration loss is detected based on the timing of the next interrupt request
signal (the eighth or ninth clock, when a stop condition is detected, etc.) and
the setting of the ALDn bit to 1, which is made by software.
For details of interrupt request timing, see“I2C Interrupt Request Signals
(INTIICn)“ on page 601.
Arbitration timing example
Preliminary User’s Manual U17566EE1V2UM00
Master 1 loses arbitration
Hi-Z
Hi-Z
I
2
C Bus (IIC)