upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 540
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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Chapter 16
540
Figure 16-13
Start bit
FL
16.6.7 Baud rate during continuous transmission
16.7 Cautions
Bit 0
FL
During continuous transmission, the transfer rate from the stop bit to the next
start bit is usually 2 base clocks longer. However, timing initialization is
performed via start bit detection by the receiving side, so this has no influence
on the transfer result.
Transfer rate during continuous transfer
Assuming 1 bit data length: FL; stop bit length: FLstp; and base clock
frequency: f
Therefore, the transfer rate during continuous transmission is as follows.
• When the clock supply to UARTAn is stopped (for example, in IDLE or STOP
Preliminary User’s Manual U17566EE1V2UM00
mode), the operation stops with each register retaining the value it had
immediately before the clock supply was stopped. The TXDAn pin output
also holds and outputs the value it had immediately before the clock supply
was stopped. However, the operation is not guaranteed after the clock
supply is resumed. Therefore, after the clock supply is resumed, the circuits
should be initialized by setting the UAnCTL0.UAnPWR,
UAnCTL0.UAnRXEn, and UAnCTL0.UAnTXEn bits to 000.
FLstp = FL + 2/f
Transfer rate = 11 × FL + (2/f
Bit 1
FL
1 data frame
UCLK
, we obtain the following equation.
UCLK
Bit 7
FL
UCLK
Parity bit
)
FL
Asynchronous Serial Interface (UARTA)
Stop bit
FLstp
Start bit
FL
Start bit of 2nd byte
Bit 0
FL
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