upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 436

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 12
436
12.3.2 Timer start and stop
Start
Stop
The timer TZn is enabled by setting TZnCTL.TZCE to 1.
The subsequent write access to register TZnR with non-zero data starts the
timer. After that, it is prepared to load the value written to register TZnR into the
reload buffer and the counter.
The following interval times are given in periods of PCLK2.
If PCLK2 is chosen as the counter clock ([TZnCTL.TZCKS] = 0), the first and
all following interrupts occur after
where
[TZnR] = contents of register TZnR
An uncertainty exists for the first interval length, if a clock with a lower
frequency is chosen ([TZnCTL.TZCKS] > 0):
where
[TZnR] = contents of register TZnR
[TZCKS] = contents of TZnCTL.TZCKS[2:0]
All following interrupts occur after:
The timer stops when TZnCTL.TZCE is cleared. This write access is not
synchronized. The timer is immediately stopped, and its registers are reset.
Preliminary User’s Manual U17566EE1V2UM00
T
([TZnR] + 1) × 2
T
interval
interval
= ([TZnR] + 1)
= ([TZnR] + 1) × 2
[TZCKS]
≤ T
[TZCKS]
interval
≤ ([TZnR] + 2) × 2
16-bit Interval Timer Z (TMZ)
[TZCKS]