upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 925

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

DBCn 316
DBPC 108
DBPSW 111
DCHCn 319
DDAHn 314
DDALn 315
Debug Function (on-chip)
Debug function (on-chip) 877
Debug Trap 224
DFEN0 94
DFEN1 96
Digital filter enable register
Digital filter enable register
Digitally filtered inputs 93
DMA (direct memory
DMA Addressing Control Regis-
DMA Channel Control Regis-
DMA Controller 309
DMA destination address regis-
DMA destination address regis-
DMA Functions 309
DMA Restart Register
DMA source address registers
DMA source address registers
DMA Transfer Count Registers
DMA Trigger Source Select
(DFEN0) 94
(DFEN1) 96
access) 309
ters n (DADCn) 317
ters n (DCHCn) 319
ters Hn (DDAHn) 314
ters Ln (DDALn) 315
(DRST) 320
Hn (DSAHn) 312
Ln (DSALn) 313
n (DBCn) 316
Register n (DTFRn) 321
Restrictions and
Code protection 339
Automatic restart
Channel priorities 325
Control registers 312
Forcible interruption 325
Forcible termination 326
Transfer completion 327
Transfer mode 328
Transfer object 324
Transfer start factors 325
Transfer type 324
Cautions 890
function 323
Preliminary User’s Manual U17566EE1V2UM00
DMAnIC 210
DRST 320
DSAHn 312
DSALn 313
DTFRn 321
Duty factor (pulse width
DWCn 274
E
ECR 112
EIPC 108
EIPSW 111
Element pointer 106
Endian configuration register
Endian format 282
Exception status flag (EP) 222
Exception trap 222
External bus properties 257
External devices
External interrupt configuration
External memory area 122
External reset 866
F
FCC 155
FEPC 108
FEPSW 111
Fixed peripheral I/O area 255
Flash area 119, 121
Flash memory 229
Flash programmer 238
Flash programming
modulation) 804
(BEC) 269
registers (INTMn) 218
Bus access 258
Bus priority order 257
Bus width 257
Initialization for
Interface timing 284
Address assignment 230
protection 339
Self-programming 234
Communication
Pin connection 242
Programming
Mode 115
via N-Wire 237
access 259
mode 239
method 244
FOUTCLK control register
G
GCCn0 447
GCCn5 447
GCCnm 448
General purpose registers (r0 to
Global pointer 106
H
HALT Mode 169
I
I
ICC 156
ID code 879
IDLE mode 170
Idle pins
Idle state insertion (access to
IIC clock control register
2
C bus 573
(FCC) 155
r31) 106
external devices) 284
with flash
Acknowledge signal 596
Address match detection
Arbitration 622
Cautions 624
Communication
Control registers 578
Definitions and control
Error detection 620
Extension code 621
Interrupt request signal
Interrupt request signals
Pin configuration 593
Stop condition 598
Timing of data
Transfer direction
Wait signal 599
Wakeup function 623
Recommended
programmer 238
method 620
operations 624
methods 594
(INTIICn) generation
timing and wait
control 619
(INTIICn) 601
communication 631
specification 596
connection 98
Index
925