upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 556

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 17
556
Shift register
17.4.4 Continuous mode (master mode, reception mode)
CBn TSF
INTCnR
CBnSCE
SCKBn
CBn RX
SOBn
SIBn
(1)
(2)
(3)
(4)
L
(8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to
To continue transfer, repeat steps (5) to (7) before (8).
In transmission mode or transmission/reception mode, the communication is
not started by reading the CBnRX register.
MSB first (CBnCTL0.CBnDIR bit = 0), communication type 2 (see 16.4 (2)
CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits
(CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0)
(1) Clear the CBnCTL0.CBnPWR bit to 0.
(2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode.
(3) Set the CBnCTL0.CBnRXE bit to 1 at the same time as specifying the
(4) Set the CBnPWR bit to 1 to enable the CSIBn operation.
(5) Perform a dummy read of the CBnRX register (reception start trigger).
(6) The reception complete interrupt request signal (INTCBnR) is output.
(7) Set the CBnCTL0.CBnSCE bit = 0 while the last data being received to set
Preliminary User’s Manual U17566EE1V2UM00
(5)
stop the operation of CSIBn (end of transmission/reception).
transfer mode using the CBnDIR bit, to set the reception enabled status.
the final receive data status.
Read the CBnRX register before the next receive data arrives or before
the CBnPWR bit is cleared to 0.
0
1
0
1
0
1
0
(6)
1
55H
1
(7)
0
55H
1
0
Clocked Serial Interface (CSIB)
1
0
1
(6)
0
AAH
AAH
(8)
00H
00H