upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 400
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
- Current page: 400 of 930
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Chapter 11
400
CCR0 buffer register
CCR1 buffer register
INTTPnCC0 signal
TPnCCR0 register
TPnCCR1 register
TOPn1 pin output
16-bit counter
TPnCE bit
(3)
FFFFH
0000H
PWM output mode operation timing
(a) Changing pulse width during operation
Preliminary User’s Manual U17566EE1V2UM00
To change the PWM waveform while the counter is operating, write the
TPnCCR1 register last.
Rewrite the TPnCCRm register after writing the TPnCCR1 register after
the INTTPnCC1 signal is detected.
To transfer data from the TPnCCRm register to the CCRm buffer register,
the TPnCCR1 register must be written.
To change both the cycle and active level of the PWM waveform at this
time, first set the cycle to the TPnCCR0 register and then set the active
level to the TPnCCR1 register.
To change only the cycle of the PWM waveform, first set the cycle to the
TPnCCR0 register, and then write the same value to the TPnCCR1
register.
To change only the active level width (duty factor) of the PWM waveform,
only the TPnCCR1 register has to be set.
After data is written to the TPnCCR1 register, the value written to the
TPnCCRm register is transferred to the CCRm buffer register in
synchronization with clearing of the 16-bit counter, and is used as the
value compared with the 16-bit counter.
To write the TPnCCR0 or TPnCCR1 register again after writing the
TPnCCR1 register once, do so after the INTTPnCC0 signal is generated.
Otherwise, the value of the CCRm buffer register may become undefined
because the timing of transferring data from the TPnCCRm register to the
CCRm buffer register conflicts with writing the TPnCCRm register.
D
10
D
D
00
00
D
10
D
D
D
10
10
D
00
00
D
10
D
00
D
D
11
16-bit Timer/Event Counter P (TMP)
01
D
01
D
11
D
D
D
11
01
11
D
01
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