upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 327

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

DMA Controller (DMAC)
DMA Transfer
Request CH1
Figure 8-4
8.11 DMA Transfer Completion
CPU
Note
Note
DSAL1, DSAH1,
DDAL1, DDAH1
EN1 bit = 1
TC1 bit = 0
CPU
The next condition can be set even during DMA transfer because the DSAn,
DDAn, and DBCn registers are buffered registers. However, the setting to the
DADCn register is invalid (refer to “Automatic Restart Function” on page 323
and “DADCn - DMA addressing control registers” on page 317).
Figure 8-4 shows a forcible termination of a block transfer operation of DMA
channel 1. A transfer containing a new configuration is executed.
DMA transfer forcible termination example 2
Since the DSALn, DSAHn, DDALn, DDAHn and DBCn registers are buffered
registers, the next transfer condition can be set even during a DMA transfer.
However, a setting in the DADCn register is ignored (refer to “Automatic
Restart Function” on page 323)
When DMA transfer ends and the TCn bit of the DCHCn register is set, a DMA
transfer end interrupt (INTDMAn) is issued to the Interrupt Controller (INTC).
Preliminary User’s Manual U17566EE1V2UM00
CPU
Set register
CPU DMA1
DSAL1, DSAH1,
DDAL1, DDAH1
DMA1
DMA1
Set register
DMA1 DMA1
DCHC1
(INIT1 bit = 1)
EN1 bit
TC1 bit = 0
DMA channel 1 transfer is forcibly
terminated and the bus is released
DMA1
Set register
→
0
CPU
CPU
DADC1,
DCHC1
EN1 bit
TC1 bit = 0
CPU
Set register
→
1
CPU DMA1
DMA1 DMA1
DMA channel 1
terminal count
EN1 bit
TC1 bit
Chapter 8
CPU
→
→
1
0
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