upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 205
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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Interrupt Controller (INTC)
Figure 5-6
Caution
5.3.2 Restore
Note
1
PC
PSW
Corresponding
bit of ISPR
Restores original processing
Recovery from maskable interrupt processing is carried out by the RETI
instruction.
When the RETI instruction is executed, the CPU performs the following steps,
and transfers control to the address of the restored PC.
(1)
(2)
Figure 5-6 illustrates the processing of the RETI instruction.
RETI instruction processing
1.
2.
When the PSW.EP bit and the PSW.NP bit are changed by the LDSR
instruction during maskable interrupt processing, in order to restore the PC
and PSW correctly during recovery by the RETI instruction, it is necessary to
set PSW.EP back to 0 and PSW.NP back to 0 using the LDSR instruction
immediately before the RETI instruction.
Preliminary User’s Manual U17566EE1V2UM00
For the ISPR register, see “ISPR - In-service priority register“ on page 216.
The solid lines show the CPU processing flow.
RETI instruction
Restores the values of the PC and the PSW from EIPC and EIPSW
because the EP bit of the PSW is 0 and the NP bit of the PSW is 0.
Transfers control to the address of the restored PC and PSW.
Note
PSW.NP
PSW.EP
0
0
EIPC
EIPSW
0
1
PC
PSW
FEPC
FEPSW
Chapter 5
205
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