upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 911

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Appendix B Registers Access Times
DMA access
CPU access
Note
Preliminary User’s Manual U17566EE1V2UM00
This chapter provides formulas to calculate the access time to registers, which
are accessed via the peripheral I/O areas.
All accesses to the peripheral I/O areas are passed over to the NPB bus via
the VSB - NPB bus bridge BBR. Read and write access times to registers via
the NPB depend on the register, the system clock VBCLK and the setting of
the VSWC register.
The CPU operation during an access to a register via the NPB depends also
on the kind of peripheral I/O area:
• Fixed peripheral I/O area
• Programmable peripheral I/O area
In the following formulas are given to calculate the access times T
CPU reads from or writes to special function registers via the NPB bus.
The access time depends
• on the CPU system clock frequency f
• on the setting of the internal peripheral function wait control register VSWC,
• for some registers on the clock frequency applied to the module
“ru[...]” in the formulas mean “round up” the calculated value of the term in
squared brackets.
All formulas calculate the maximum access time.
For calculating the access times for CPU accesses 1 VBLCK period time 1/
f
For accesses of the DMA Controller the given formulas calculate the exact
values.
VBCLK
During a read or write access the CPU operation stops until the access via
the NPB is completed.
During a read access the CPU operation stops until the read access via the
NPB is completed.
During a write access the CPU operation continues operation, provided any
preceded NPB access is already finished. If a preceded NPB access is still
ongoing the CPU stops until this access is finished and the NPB is cleared.
which determines the address set up wait SUWL = VSWC.SUWL and data
wait VSWL = VSWC.VSWL (refer to “VSWC - Peripheral function wait
control register“ on page 234 for the correct values for a certain CPU
system clock VBCLK)
has to be added to the results of the formulas.
VBCLK
a
, when the
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