upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 621

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

I
2
C Bus (IIC)
Table 18-5
18.11 Extension Code
• When the higher 4 bits of the receive address are either 0000 or 1111, the
• If 11110xx0 is set to the SVAn register by a 10-bit address transfer and
• Since the processing after the interrupt request signal occurs differs
Extension code bit definitions
Preliminary User’s Manual U17566EE1V2UM00
extension code flag (IICSn.EXCn bit) is set for extension code reception and
an interrupt request signal (INTIICn) is issued at the falling edge of the
eighth clock.
The local address stored in the SVAn register is not affected.
11110xx0 is transferred from the master device, the results are as follows.
Note that the INTIICn signal occurs at the falling edge of the eighth clock
– Higher four bits of data match: EXCn bit = 1
– Seven bits of data match:
according to the data that follows the extension code, such processing is
performed by software.
For example, when operation as a slave is not desired after the extension
code is received, set the IICCn.LRELn bit to 1 and the CPU will enter the
next communication wait state.
Slave Address
0000
0000
0000
0000
1111
000
000
001
010
0xx
R/W Bit
X
X
X
0
1
Description
General call address
Start byte
CBUS address
Address that is reserved for different bus format
10-bit slave address specification
IICSn.COIn bit = 1
Chapter 18
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