upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 412
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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Chapter 11
412
INTTPnCC0 signal
INTTPnCC1 signal
TPnCCR0 register
TPnCCR1 register
TOPn1 pin output
TOPn pin output
16-bit counter
TPnCE bit
(3)
FFFFH
0000H
Operation timing in free-running timer mode
(a) Interval operation with compare register
Preliminary User’s Manual U17566EE1V2UM00
When 16-bit timer/event counter P is used as an interval timer with the
TPnCCRm register used as a compare register, software processing is
necessary for setting a comparison value to generate the next interrupt
request signal each time the INTTPnCCm signal has been detected.
When performing an interval operation in the free-running timer mode, two
intervals can be set with one channel.
To perform the interval operation, the value of the corresponding
TPnCCRm register must be re-set in the interrupt servicing that is
executed when the INTTPnCCm signal is detected.
The set value for re-setting the TPnCCRm register can be calculated by
the following expression, where “D
Compare register default value: D
Value set to compare register second and subsequent time:
Previous set value + D
(If the calculation result is greater than FFFFH, subtract 10000H from the
result and set this value to the register.)
Interval period
Interval period
D
(D
(D
00
00
D
10
D
+ 1)
10
+ 1)
D
00
10
Interval period
(10000H +
D
01
Interval period
− D
(10000H +
D
D
D
00
11
01
)
m
01
− D
D
Interval period
10
D
11
)
(D
11
02
− D
D
Interval period
02
01
D
(10000H +
)
D
02
12
m
Interval period
− D
m
(10000H +
– 1
” is the interval period.
D
D
16-bit Timer/Event Counter P (TMP)
D
11
03
12
)
12
− D
D
03
02
D
)
Interval period
03
(10000H +
D
Interval period
13
(10000H +
D
− D
04
D
− D
D
12
13
)
D
13
03
04
)
D
04
D
D
14
05
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