upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 450

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 13
450
Match and
CCSGn0
Free-run
mode
mode
clear
0
1
Register setting value
Table 13-8
TBGnm
0
13.6 Explanation of Basic Operation
Note
(1)
SWFGnm
0
1
0
1
Overview of the mode settings
The Timer Gn includes 2 channels of 16-bit counters (TMGn0/TMGn1), which
can operate as independently timebases. TMGn0 (TMGn1) can be set by
CCSGn0 bit (CCSGn5 bit) in the following modes:
• free-run mode
• match and clear mode
When a timer output (TOGnm) or INTCCGnm interrupt is used, one of the two
counters can be selected by setting the TBGnm bit (m = 1 to 4) of the
TMGCMHn register.
The tables below indicate the interrupt output and timer output states
dependent on the register setting values.
Interrupt output and timer output states dependent on the register
setting values
1.
2.
3.
Preliminary User’s Manual U17566EE1V2UM00
An interrupt is generated only when the value of the GCCn0 register is
FFFFH.
An interrupt is generated only when the value of the GCCn0 register is not
FFFFH.
The setting of the CCSGnm bit in combination with the SWFGnm bit sets
the mode for the timing of the actualization of new compare values.
•
•
In compare mode the new compare value will be immediately active.
In PWM mode the new compare value will be active first after the next
overflow or match & clear of the assigned counter (TMGn0, TMGn1).
CCSGnm
0
1
0
1
0
1
0
1
interrupt
INTTMGn0
Overflow
Overflow
interrupt
Note 1
match
INTCCGn0
detection
TI0 edge
GCCn0
State of each output pin
Note 2
16-bit Multi-Purpose Timer G (TMG)
CMPGm match
CMPGm match
GCCnm match
GCCnm match
INTCCGnm
TIm edge
TIm edge
TIm edge
TIm edge
detection
detection
detection
detection
(match and clear)
Tied to inactive
Tied to inactive
(free run)
TOGnm
PWM
PWM
level
level