upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 358

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 11
358
Operation
Interval timer mode
External event count
mode
External trigger pulse
output mode
One-shot pulse output
mode
PWM output mode
Free-running timer mode Invalid
Pulse width
measurement
mode
Note 1
Note 2
Note 2
Count clock
selection
Figure 11-2
Note 2
11.5.1 Interval timer mode (TPnMD2 to TPnMD0 = 000)
11.5 Operation
Note
TPnCE bit
TMPn can perform the following operations.
1.
2.
In the interval timer mode, an interrupt request signal (INTTPnCC0) is
generated at the specified interval if the TPnCTL0.TPnCE bit is set to 1. A
square wave whose half cycle is equal to the interval can be output from the
TOPn0 pin.
Usually, the TPnCCR1 register is not used in the interval timer mode.
Configuration of interval timer
Preliminary User’s Manual U17566EE1V2UM00
TPnCTL1.TPnEST Bit
(Software Trigger Bit)
Invalid
Invalid
Valid
Valid
Invalid
Invalid
To use the external event count mode, specify that the valid edge of the
TIPn0 pin capture trigger input is not detected (by clearing the
TPnIOC1.TPnIS1 and TPnIOC1.TPnIS0 bits to “00”).
When using the external trigger pulse output mode, one-shot pulse output
mode, and pulse width measurement mode, select the internal clock as the
count clock (by clearing the TPnCTL1.TPnEEE bit to 0).
CCR0 buffer register
TPnCCR0 register
TIPn0 Pin
(Ext. Trigger Input)
Invalid
Invalid
Valid
Valid
Invalid
Invalid
Invalid
16-bit counter
Clear
Match signal
16-bit Timer/Event Counter P (TMP)
Capture/ Compare
Register Setting
Compare only
Compare only
Compare only
Compare only
Compare only
Switching enabled
Capture only
controller
Output
INTTPnCC0 signal
Compare Register
Write
Anytime write
Anytime write
Batch write
Anytime write
Batch write
Anytime write
Not applicable
TOPn0 pin