upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 782
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
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Chapter 20
782
20.4.2 Trigger mode
(1)
(2)
The timing of starting the conversion operation is specified by setting a trigger
mode. The trigger mode includes a software trigger mode and hardware trigger
modes. The hardware trigger modes include timer trigger modes 0 and 1, and
external trigger mode. The ADA0TMD bit of the ADA0M0 register is used to set
the trigger mode. In timer trigger mode set ADA0M2.ADA0TMD[1:0] = 01.
Software trigger mode
When the ADA0CE bit of the ADA0M0 register is set to 1, the signal of the
analog input pin ANIn specified by the ADA0S register is converted. When
conversion is complete, the result is stored in the ADCR0n register. At the
same time, the A/D conversion end interrupt request signal (INTAD) is
generated.
If the operation mode specified by the ADA0MD1 and ADA0MD0 bits of the
ADA0M0 register is the continuous select/scan mode, the next conversion is
started, unless the ADA0CE bit is cleared to 0 after completion of the first
conversion.
When conversion is started, the ADA0EF bit is set to 1 (indicating that
conversion is in progress).
If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written
during conversion, the conversion is aborted and started again from the
beginning.
Timer trigger mode
In this mode, converting the signal of the analog input pin ANIn specified by the
ADA0S register is started by the Timer Z underflow interrupt signal.
Make sure to set ADA0M2.ADA0TMD[1:0] = 01
When conversion is completed, the result of the conversion is stored in the
ADCR0n register. At the same time, the A/D conversion end interrupt request
signal (INTAD) is generated, and the A/D Converter waits for the trigger again.
When conversion is started, the ADA0EF bit is set to 1 (indicating that
conversion is in progress). While the A/D Converter is waiting for the trigger,
however, the ADA0EF bit is cleared to 0 (indicating that conversion is stopped).
If the valid trigger is input during the conversion operation, the conversion is
aborted and started again from the beginning.
If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written
during conversion, the conversion is stopped and the A/D Converter waits for
the trigger again.
Preliminary User’s Manual U17566EE1V2UM00
B
.
A/D Converter (ADC)
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