upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 444
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
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Chapter 13
444
Bit position
15 to 12
11 to 0
Initial Value
Table 13-5
Address
Access
Bit name
IEGny1,
TBGnm
IEGny0
(2)
TMGCMn - Timer Gn channel mode register
This register specifies the assigned counter (TMGn0 or TMGn1) for the
GCCnm register.
Furthermore it specifies the edge detection for the TIGny-input-pins.
This register can be read/written in 16-bit, 8-bit or 1-bit units.
The low byte TMGCMn.bit[7:0] is accessible separately under the name
TMGCMnL, the high byte TMGCMn.bit[15:8] under the name TMGCMnH.
TMGCMn, TMGCMnL: <base> + 2
TMGCMnH:
0000
TMGCMn register contents
Preliminary User’s Manual U17566EE1V2UM00
IEGn31
TBGn4
R/W
R/W
Function
Assigns Capture/Compare registers GCCn1 to GCCn4 to one of the 2 counters
TMGn0 or TMGn1:
Specifies the valid edge of external capture signal input pin (TIGnm) for the capture
register performing capture-match with the assigned counter TMGn0 or TMGn1:
15
7
0: Set TMGn0 as the corresponding counter to GCCnm register and TIGnm/
1: Set TMGn1 as the corresponding counter to GCCnm register and TIGnm/
H
. This register is cleared by any reset.
TOGnm-pin
TOGnm-pin
IEGny1
0
0
1
1
IEGn30
TBGn3
R/W
R/W
14
6
IEGny0
IEGn21
TBGn2
0
1
0
1
R/W
R/W
13
<base> + 3
5
Valid edge
Falling edge
Rising edge
No edge detection performed
Both rising and falling edges
IEGn20
TBGn1
R/W
R/W
12
4
H
H
16-bit Multi-Purpose Timer G (TMG)
IEGn51
IEGn11
R/W
R/W
11
3
IEGn50
IEGn10
R/W
R/W
10
2
IEGn41
IEGn01
R/W
R/W
9
1
IEGn40
IEGn00
R/W
R/W
8
0
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