upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 480

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 14
a)
480
4 MHz main osc.
32 KHz sub osc.
240 KHz ring osc.
Clock source
The maximum period corresponds to a counter load value of 2
Table 14-1
14.1.2 Principle of operation
Note
(1)
(2)
Clock divider setting
In order to generate an interrupt every one or two seconds, WTCLK is usually
set to a frequency around 30 KHz. Then, a load value around 2
running time of about 1 s.
Operation control of WT0
The source and frequency of WTCLK are specified in the Clock Generator
register TCC.
The Clock Generator contains a programmable frequency divider that makes it
possible to scale down the selected clock source.
WTCLK uses the same clock source and clock divider as the LCD Controller/
Driver clock LCDCLK. The frequency f
f
Typical settings and the resulting maximum time interval between two
interrupts are listed in the table below.
Typical Settings of WTCLK
Note that you can double the maximum period by setting TCC.WTSEL1 to 1.
The clock input can be disabled (WT0CTL.WTCE = 0). This stops the Watch
Timer. After reset, the timer is also stopped.
When WT0 is enabled and a non-zero reload value is specified, the counter
decreases with every rising edge of WTCLK. When the counter reaches zero,
the interrupt INTWT0UV is active high for one clock cycle. Upon undeflow, i.e.
with the next clock, the timer reloads its start value and resumes down-
counting. The load value can be freely chosen
Operation of WT1
Once WT1 is enabled and a non-zero reload value is specified, its counter
decreases with every interrupt INTWT0UV.
When WT1 reaches zero, it generates the interrupt INTWT1UV. Upon
undeflow, i.e. with the next clock, the timer reloads its load value and restarts
down-counting. The load value can be freely chosen.
Starting WT1 requires some attention. For further details refer to “Watch Timer
start-up“ on page 486.
Preliminary User’s Manual U17566EE1V2UM00
LCDCLK
1 / 128
1 / 8
/ 2. For details refer to “Clock Generator“ on page 129.
1
WTCLK Frequency
32.768 KHz (typ.)
30 KHz (typ.)
31.25 KHz
16
WTCLK
– 1.
can be the same as f
Max. period of INTWT0UV
2.184533 s
Watch Timer (WT)
2.097 s
2.0 s
15
will yield a
LCDCLK
or
a