upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 447
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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16-bit Multi-Purpose Timer G (TMG)
Compare mode
Capture mode
Initial Value
Address
Caution
Access
(6)
GCCn0, GCCn5 - Timer Gn capture/compare registers of the 2 counters
The GCCn0, GCCn5 registers are 16-bit capture/compare registers of Timer
Gn. These registers are fixed assigned to the counter registers:
• GCCn0 is fixed assigned to timebase TMGn0
• GCCn5 is fixed assigned to timebase TMGn1
In the capture register mode, GCCn0 (GCCn5) captures the TMGn0 (TMGn1)
count value if an edge is detected at Pin TIGn0 (TIGn5).
In the compare register mode, GCCn0 (GCCn5) detects match with TMGn0
(TMGn1) and clears the assigned Timebase. So this “match and clear mode”
is used to reduce the number of valid bits of the counter TMGn0 (TMGn1).
If in Compare Mode write to this registers before POWERn and ENFGnx bit
are "1" at the same time.
In capture mode, these registers can be read in 16-bit units.
In compare mode, these registers can be read/written in 16-bit units.
GCCn0:
GCCn5:
0000
Preliminary User’s Manual U17566EE1V2UM00
15
H
14
. These registers are cleared by any reset.
<base> + C
<base> + 16
13
12
11
H
H
10
GGCn0/GGCn5 value
9
8
R/W
7
6
5
4
3
2
Chapter 13
1
447
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