upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 182

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 4
182
After IDLE and
After WATCH
Table 4-30
STOP
Note that CGSTAT.CMPLPSM is set to 0 if a power save mode request is
accepted. If it was 0 before it does not change it’s state.
Table 4-30 summarizes the different configurations.
Power save mode wake-up configurations
a)
b)
If the power save mode request was accepted the entire clock generator can
be reconfigured after wake-up. Afterwards set CKC.PLLEN = 1 and
CKC.SCEN = 1 and wait the stabilization times before using the PLL and
SSCG as clock sources.
On return from IDLE or STOP mode, the bits PCC.CLS, PCC.CKS1, and
PCC.CKS2 are cleared. After IDLE mode, the main oscillator is still running; on
return from STOP mode, it is automatically started.
As a result, the main oscillator is chosen and enabled as the source for the
CPU system clock VBCLK.
In WATCH mode the main oscillator operation depends on PSM.OSCDIS:
• If PSM.OSCDIS was 0 before entering WATCH mode the main oscillator
• If PSM.OSCDIS was 1 before entering WATCH mode the main oscillator is
Preliminary User’s Manual U17566EE1V2UM00
before PSM-RQ
– CGSTAT.CMPLPSM = 1 if a power save mode has been completely
remains active. After WATCH mode release the main oscillator is chosen as
the CPU system clock.
stopped during WATCH mode. After WATCH mode release the main
SSCG operating (provided that CGSTAT.CMPLPSM
save mode request)
entered, wake-up configuration established, PLL/SSCG stopped
(provided that a power save mode request has been accepted before, i.e.
CGSTAT.CMPLPSM
A change of a register’s contents can only be taken as an indicator if it is before
power save mode request different to the wake-up configuration.
PSM-RQ: power save mode request (PSC.STP = 1)
CGSTAT.CMPLPSM
0
1
b
after wake-up
0
1
0
1
=
1
→
Registers and
0)
clock paths
not changed
not changed
not changed
not changed
changed
changed
changed
changed
a
Configuration after wake-up
PSM-RQ not accepted
PSM-RQ accepted
configuration done, but PLL/
SSCG operating
not possible
PSM-RQ accepted
configuration done, PLL/SSCG
off
not possible
PSM-RQ accepted
configuration done, but PLL/
SSCG operating
PSM-RQ not accepted
PSM-RQ accepted
configuration done, PLL/SSCG
off
=
1 before power
Clock Generator