upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 438

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 13
438
13.2 Function Overview of Each Timer Gn
Note
• 16-bit timer/counter (TMGn0, TMGn1): 2 channels
• Bit length
• Capture/compare register (GCCny): 6
• Count clock division selectable by prescaler (frequency of peripheral clock:
• Interrupt request sources
• PWM output function
• Output delay operation
• Edge detection and noise elimination filter
The TIGn1 to TIGn4 and TOGn1 to TOGn4 are each alternative function pins.
The following figure shows the block diagram of Timer Gn.
Preliminary User’s Manual U17566EE1V2UM00
– Timer Gn registers (TMGn0, TMGn1): 16 bits
– 16-bit
– 2 registers are assigned fix to the corresponding one of the 2 counters
– 4 free assignable registers to one of the 2 counters
f
– In 8 steps from f
– Edge detection circuit with noise elimination.
– Compare-match interrupt requests: 6 types
– Timer counter overflow interrupt requests: 2 types
– In match and clear mode the INTTMGn0 (INTTMGn1) interrupt is
– Control of the outputs of TOGn1- through TOGn4-pin in the compare
– A clock-synchronized output delay can be added to the output signal of
– This is effective as an EMI counter measure.
– External signals shorter than 1 count clock (f
SPCLK0
Perform comparison of capture/compare register with one of the 2
counters (TMGn0, TMGn1) and generate the INTCCGny (y = 0 to 5)
interrupt upon compare match.
In free run mode the INTTMGn0 (INTTMGn1) interrupt is generated when
the count value of TMGn0 (TMGn1) toggles from FFFFH to 0000H.
generated when the count value of TMGn0 (TMGn1) matches the GCC0
(GCC1) value.
mode. PWM output can be performed using the compare match timing of
the GCCn1 to GCCn4 register and the corresponding timebase (TMGn0,
TMGn1).
pins TOGn1 to TOGn4.
eliminated as noise.
= 16 MHz)
SPCLK0
/2 to f
SPCLK0
16-bit Multi-Purpose Timer G (TMG)
/256
COUNTn
, not f
SPCLK0
) are