upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 216

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 5
216
Bit position
Bit position
PSW
ISPR
7 to 0
5
31
0
ISPR7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP
7
5.3.6 ISPR - In-service priority register
5.3.7 Maskable interrupt status flag (ID)
Bit name
Bit name
ISPR7 to
Note
ISPR0
ID
ISPR6
6
This register holds the priority level of the maskable interrupt currently
acknowledged. When an interrupt request is acknowledged, the bit of this
register corresponding to the priority level of that interrupt request is set to 1
and remains set while the interrupt is serviced.
When the RETI instruction is executed, the bit corresponding to the interrupt
request having the highest priority is automatically reset to 0 by hardware.
However, it is not reset to 0 when execution is returned from non-maskable
interrupt servicing or exception processing.
This register is read-only in 8-bit or 1-bit units.
n = 0 to 7 (priority level)
The ID flag is bit 5 of the PSW and this controls the maskable interrupt’s
operating state, and stores control information regarding enabling or disabling
of interrupt requests.
Preliminary User’s Manual U17566EE1V2UM00
Function
Indicates priority of interrupt currently acknowledged
Function
Indicates whether maskable interrupt processing is enabled or disabled.
This bit is set to 1 by the DI instruction and reset to 0 by the EI instruction. Its value
is also modified by the RETI instruction or LDSR instruction when referencing to
PSW.
Non-maskable interrupt requests and exceptions are acknowledged regardless of
this flag. when a maskable interrupt is acknowledged, the ID flag is automatically
set to 1 by hardware.
The interrupt request generated during the acknowledgement disabled period
(ID = 1) is acknowledged when the PIFn bit of PICn register is set to 1, and the ID
flag is reset to 0.
ISPR5
0: Interrupt request with priority n not acknowledged
1: Interrupt request with priority n acknowledged
0: Maskable interrupt request acknowledgement enabled
1: Maskable interrupt request acknowledgement disabled (pending)
5
ISPR4
4
ISPR3
3
ISPR2
8
2
7
ISPR1
EP
6
1
ID
5
ISPR0
SAT
4
0
Interrupt Controller (INTC)
CY
3
FFFFF19AH
OV
2
Address
1
S
0
Z
Initial value
00000020H
value
Initial
00H