upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 623

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

I
2
Status During Arbitration
Transmitting address transmission
Read/write data after address transmission
Transmitting extension code
Read/write data after extension code transmission
Transmitting data
ACK signal transfer period after data reception
When restart condition is detected during data
transfer
When stop condition is detected during data
transfer
When SDAn pin is low level while attempting to
output restart condition
When stop condition is detected while attempting
to output restart condition
When DSA0n pin is low level while attempting to
output stop condition
When SCLn pin is low level while attempting to
output restart condition
C Bus (IIC)
Table 18-6
18.13 Wakeup Function
Note
Status during arbitration and interrupt request signal generation timing
1.
2.
The I
signal (INTIICn) when a local address and extension code have been received.
This function makes processing more efficient by preventing unnecessary
interrupt request signals from occurring when addresses do not match.
When a start condition is detected, wakeup stand-by mode is set. This wakeup
stand-by mode is in effect while addresses are transmitted due to the
possibility that an arbitration loss may change the master device (which has
output a start condition) to a slave device.
However, when a stop condition is detected, the IICCn.SPIEn bit is set
regardless of the wakeup function, and this determines whether interrupt
request signals are enabled or disabled.
Preliminary User’s Manual U17566EE1V2UM00
When the IICCn.WTIMn bit = 1, an interrupt request signal occurs at the
falling edge of the ninth clock. When the WTIMn bit = 0 and the extension
code’s slave address is received, an interrupt request signal occurs at the
falling edge of the eighth clock.
When there is a possibility that arbitration will occur, set the SPIEn bit to 1
for master device operation.
2
C bus slave function is a function that generates an interrupt request
Interrupt Request Generation Timing
At falling edge of eighth or ninth clock following byte
transfer
When stop condition is output (when
IICCn.SPIEn bit = 1)
At falling edge of eighth or ninth clock following byte
transfer
When stop condition is output (when
IICCn.SPIEn bit = 1)
At falling edge of eighth or ninth clock following byte
transfer
Note 1
Note 1
Note 1
Note 2
Note 2
Chapter 18
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