upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 381

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

16-bit Timer/Event Counter P (TMP)
<1> Count operation start flow
<2> TPnCCR0 and TPnCCR1 register
setting change flow
(TPnCKS0 to TPnCKS2 bits)
Setting of TPnCCR0 register
Setting of TPnCCR1 register
Figure 11-17
Register initial setting
TPnCE bit = 1
TPnCCR0,
TPnCTL1,
TPnIOC0,
TPnIOC2,
TPnCCR1
TPnCTL0
START
(3)
Software processing flow in external trigger pulse output mode (2/2)
External trigger pulse output mode operation timing
(a) Note on changing pulse width during operation
Preliminary User’s Manual U17566EE1V2UM00
To change the PWM waveform while the counter is operating, write the
TPnCCR1 register last.
Rewrite the TPnCCRm register after writing the TPnCCR1 register after
the INTTPnCC0 signal is detected.
Initial setting of these
registers is performed
before setting the
TPnCE bit to 1.
The TPnCKS0 to
TPnCKS2 bits can be
set at the same time
when counting is
enabled (TPnCE bit = 1).
Trigger wait status
TPnCCR1 register write
processing is necessary
only when the set
cycle is changed.
When the counter is
cleared after setting,
the value of the TPnCCRm
register is transferred to
the CCRm buffer register.
<3> PnCCR0, TPnCCR1 register
<4> PnCCR0, TPnCCR1 register
<5> Count operation stop flow
setting change flow
setting change flow
Setting of TPnCCR1 register
Setting of TPnCCR0 register
Setting of TPnCCR1 register
TPnCE bit = 0
STOP
Counting is stopped.
Only writing of the TPnCCR1
register must be performed when
When the counter is cleared after
setting, the value of the
TPnCCRm register is transferred
to the CCRm buffer register.
When the counter is
cleared after setting,
the value of the TPnCCRm
register is transferred to
the CCRm buffer register.
the set duty factor is changed.
Chapter 11
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