upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 222

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 5
222
Bit position
PSW
6
15
× × × × × 1
31
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP
5.5.3 Exception status flag (EP)
5.6.1 Illegal opcode definition
Bit name
Note
5.6 Exception Trap
11 10
EP
(1)
1 1
The EP flag is bit 6 of PSW, and is a status flag used to indicate that exception
processing is in progress. It is set when an exception occurs.
An exception trap is an interrupt that is requested when an illegal execution of
an instruction takes place. For this microcontroller, an illegal opcode exception
(ILGOP: Illegal Opcode Trap) is considered as an exception trap.
The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode
(bits 23 to 26) of 0111B to 1111B, and a sub-opcode (bit 16) of 0B. An
exception trap is generated when an instruction applicable to this illegal
instruction is executed.
×: Arbitrary
Operation
If an exception trap occurs, the CPU performs the following processing, and
transfers control to the handler routine:
(1)
(2)
(3)
(4)
Figure 5-12 illustrates the processing of the exception trap.
Preliminary User’s Manual U17566EE1V2UM00
Shows that exception processing is in progress.
0: Exception processing not in progress.
1: Exception processing in progress.
Saves the restored PC to DBPC.
Saves the current PSW to DBPSW.
Sets the NP, EP, and ID bits of the PSW.
Sets the handler address (00000060H) corresponding to the exception
trap to the PC, and transfers control.
1
1
5 4
1 × × × × × × × × × ×
0 31
8
7
Function
EP
6
27 26
0
1
ID
5
1 1
1 1
to
SAT
4
Interrupt Controller (INTC)
23 22
1
1
CY
3
× × × × × ×
OV
2
1
S
0
Z
Initial value
00000020H
16
0