upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 183

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Clock Generator
After Sub-WATCH
After HALT
In Sub-WATCH mode the main oscillator is stopped. On return from Sub-
WATCH, PCC.CLS is set to the status of PSM.OSCDIS.
• If PSM.OSCDIS was 0 before entering Sub-WATCH, the main oscillator is
• If PSM.OSCDIS was 1 before entering Sub-WATCH, the main oscillator
“Sub clock” means the clocks supplied by either the 32 KHz sub oscillator or
the 200 KHz ring oscillator. The selection must be made in the PCC register
before entering the Sub-WATCH or WATCH mode:
• PCC.SOSCP = 0: Ring oscillator
• PCC.SOSCP = 1: Sub oscillator
Software can switch from sub clock CPU operation to normal run mode (by
enabling the main oscillator by PSM.OSCDIS = 0) or re-enter Sub-WATCH
respectively WATCH mode.
On return from HALT mode the CPU resumes operation with the same clock
settings as before HALT was entered.
Preliminary User’s Manual U17566EE1V2UM00
oscillator is automatically started, the oscillator stabilization time is waited
and the main oscillator is chosen as the CPU system clock.
started and chosen as the source for the CPU system clock (PCC.CLS = 0,
PCC.CKS[1:0] = 00
remains stopped, and the CPU is clocked by a sub clock (PCC.CLS = 1,
PCC.CKS[1:0] = xx
B
B
).
).
Chapter 4
183