upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 165

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Clock Generator
Bit position
0
Initial Value
Initial Value
Table 4-22
Address
Address
Caution
Access
Access
Bit name
Note
CLMES
(3)
(4)
CLMS - Sub oscillator clock monitor register
The 8-bit CLMS register is used to enable the monitor for the sub oscillator
clock.
This register can be read/written in 8-bit or 1-bit units.
Writing to this register is protected by a special sequence of instructions.
Please refer to “PRCMDCMS - CLMS write protection register” on page 165
for details.
FFFF F878
00
CLMS register contents
Setting CLMS.CLMES to 1 does not start the sub oscillator clock monitor. To
start the clock monitor CLMCS.CMRT has to be set to 1 afterwards.
CLMCS.CMRT must not be set before the sub oscillator has stabilized.
PRCMDCMS - CLMS write protection register
The 8-bit PRCMDCMS register protects the register CLMS from inadvertent
write access, so that the system does not stop in case of a program hang-up.
After data has been written to the PRCMDCMS register, the first write access
to register CLMS is valid. All subsequent write accesses are ignored. Thus, the
value of CLMS can only be rewritten in a specified sequence, and illegal write
access is inhibited.
This register can only be written in 8-bit units.
FFFF FCB2
The contents of this register is undefined.
After writing to the PRCMDCMS register, you are permitted to write once to
CLMS. The write access to CLMS must happen with the immediately following
instruction.
In case a high level programming language is used, make sure that the
compiler translates the two write instructions to PRCMDCMS and CLMS into
two consecutive assembler “store” instructions.
Preliminary User’s Manual U17566EE1V2UM00
H
. The register is initialized by any reset.
R
7
0
W
Function
Clock monitor enable:
This bit can only be cleared by reset.
X
7
0: Clock monitor
1: Clock monitor for sub oscillator enabled.
H
H
.
R
6
0
W
6
X
for
R
5
0
W
X
5
sub oscillator disabled.
R
4
0
W
X
4
R
3
0
W
X
3
R
2
0
W
2
X
R
1
0
W
X
1
Chapter 4
CLMES
R/W
0
W
X
0
165