upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 259

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Bus and Memory Control (BCU, MEMC)
Caution
7.2.7 Initialization for access to external devices
7.2.8 External bus mute function
To enable access to external devices, initialize the following registers after any
reset.
1. Chip area select control registers CSCn
2. Bus cycle type configuration registers BCTn
3. LOcal bus size configuration register LBS
4. Data wait control registers DWCn
5. Bus cycle control register BCC
6. Page ROM configuration register PRC
7. Endian configuration register (BEC)
8. Address setup wait control register (ASC)
9. Read delay control register (RDDLY)
1.
2.
If no access via the external memory interface is performed the external bus is
set into a mute status. During mute the external bus interface pins take
following states:
• A[22:0]: hold the address of the last external access
• D[31:0]: 3-state
• WR, RD, CS0, CS1, CS3, CS4: high level (inactive state)
Preliminary User’s Manual U17566EE1V2UM00
Do not change these registers after initialization.
Do not access external devices before initialization is finished.
Define the memory banks that are allocated to external devices. Memory
banks that are not allocated to external devices, must be deactivated.
Specify the external devices that are connected to the microcontroller
device. For memory banks that are not allocated to external devices, the
corresponding bits in registers BCT0 and BCT1 should be reset.
Set the data bus width for the active chip select areas.
Set the number of data wait states with respect to the starting bus cycle.
Set the number of idle states for each chip select area.
If page ROM mode is selected (BCTn.BTk0 = 1), set whether a page ROM
cycle is on-page or off-page.
Set the endian format for each chip select area.
Set the number of address setup wait states for each chip select area.
Activate the delay of the rising edge of RD strobe, as required.
Chapter 7
259