upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 163
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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Clock Generator
Bit position
0
Initial Value
Table 4-21
Address
Access
4.2.5 Clock monitor registers
Bit name
CLMEM
Note
(1)
The following registers are used to control the monitor circuits of the main
oscillator clock and the sub oscillator clock.
Please refer to “Operation of the Clock Monitors” on page 185 for
supplementary information.
CLMM - Main oscillator clock monitor mode register
The 8-bit CLMM register is used to enable the monitor for the main oscillator
clock.
This register can be read/written in 8-bit or 1-bit units.
Writing to this register is protected by a special sequence of instructions.
Please refer to “PRCMDCMM - CLMM write protection register” on page 164
for details.
FFFF F870
00
CLMM register contents
CLMM.CLMEM can be set at any time. However, the clock monitor is only
activated after the main oscillator has stabilized, indicated by
CGSTAT.OSCSTAT = 1.
Preliminary User’s Manual U17566EE1V2UM00
H
. This register is cleared by any reset.
R
7
0
Function
Clock monitor enable:
This bit can only be cleared by reset.
0: Clock monitor
1: Clock monitor for main oscillator enabled.
H
.
R
6
0
for
R
5
0
main oscillator disabled.
R
4
0
R
3
0
R
2
0
R
1
0
Chapter 4
CLMEM
R/W
0
163
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