upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 314
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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DDAH0
DDAH1
DDAH2
DDAH3
Chapter 8
314
Bit position
11 to 0
15
15
15
15
15
IR
IR
IR
IR
14
14
14
14
0
0
0
0
Caution
Bit name
8.3.2 DMA destination address registers
13
13
13
13
0
0
0
0
DA27 to
DA16
(1)
IR
12
12
12
12
0
0
0
0
These registers are used to set the DMA destination address (28 bits each) for
DMA channel n. They are divided into two 16-bit registers, DDAHn and
DDALn.
Since these registers are configured as 2-stage FIFO buffer registers, a new
destination address for DMA transfer can be specified during DMA transfer
(refer to “Automatic Restart Function” on page 323).
DMA transfers of misaligned 16-bit/32-bit data is not supported.
DDAHn - DMA destination address registers Hn
These registers can be read/written in 16-bit units.
Preliminary User’s Manual U17566EE1V2UM00
DA27
DA27
DA27
DA27
11
11
11
11
Function
Specifies the DMA destination address.
Sets the DMA destination addresses (A27 to A16). During DMA transfer, it stores
the next DMA transfer destination address.
DA26
DA26
DA26
DA26
10
10
10
10
0: External memory or On-chip peripheral I/O
1: Internal RAM
DA25
DA25
DA25
DA25
9
9
9
9
DA24
DA24
DA24
DA24
8
8
8
8
DA23
DA23
DA23
DA23
7
7
7
7
DA22
DA22
DA22
DA22
6
6
6
6
DA21
DA21
DA21
DA21
5
5
5
5
DA20
DA20
DA20
DA20
4
4
4
4
DA19
DA19
DA19
DA19
3
3
3
3
DA18
DA18
DA18
DA18
2
2
2
2
DMA Controller (DMAC)
DA17
DA17
DA17
DA17
1
1
1
1
DA16
DA16
DA16
DA16
0
0
0
0
FFFFF086H
FFFFF08EH
FFFFF096H
FFFFF09EH
Address
Address
Address
Address
undef.
undef.
undef.
undef.
value
value
value
value
Initial
Initial
Initial
Initial
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