upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 351

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

16-bit Timer/Event Counter P (TMP)
Bit position
3 to 2
1 to 0
Initial Value
Table 11-7
Address
Caution
Access
TPnEES[1:0]
TPnETS[1:0]
Bit name
(5)
TPnIOC2 - TMPn I/O control register 2
The TPnIOC2 register is an 8-bit register that controls the valid edge of the
external event count input signal (TIPn0 pin) and external trigger input signal
(TIPn0 pin).
This register can be read/written in 8-bit or 1-bit units.
<base> + 4
00
TPnIOC2 register contents
1.
2.
Preliminary User’s Manual U17566EE1V2UM00
H
Rewrite the TPnEES1, TPnEES0, TPnETS1, and TPnETS0 bits when the
TPnCTL0.TPnCE bit = 0. (The same value can be written when the TPnCE
bit = 1.) If rewriting was mistakenly performed, clear the TPnCE bit to 0 and
then set the bits again.
The TPnEES1 and TPnEES0 bits are valid only when the
TPnCTL1.TPnEEE bit = 1 or when the external event count mode
(TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 bits = 001) has been set.
R/W
. This register is initialized by any reset.
7
0
Function
External event count input signal (TIPn0 pin) valid edge setting:
Capture trigger input signal (TIPn0 pin) valid edge setting:
TPnEES1
TPnETS1
H
0
0
1
1
0
0
1
1
R/W
6
0
TPnEES0 External event count valid edge of TIPn0
TPnETS0 External trigger input valid edge of TIPn0
R/W
5
0
0
1
0
1
0
1
0
1
No edge detection (external event invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
No edge detection (external trigger invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
R/W
4
0
TPnEES1
R/W
3
TPnEES0
R/W
2
TPnETS1
R/W
1
Chapter 11
TPnETS0
R/W
0
351