upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 560

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 17
560
Shift register
INTCBnR
CBnSCE
CBnTSF
SCKBn
CBnRX
SIBn
17.4.7 Continuous mode (slave mode, reception mode)
(1)
(2)
(3)
(4)
(5)
MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (see 16.4 (2)
CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits
(CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0)
(1) Clear the CBnCTL0.CBnPWR bit to 0.
(2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode.
(3) Set the CBnCTL0.CBnRXE and CBnCTL0.CBnSCE bits to 1 at the same
(4) Set the CBnPWR bit = 1 to enable CSIBn operation.
(5) Perform a dummy read of the CBnRX register (reception start trigger).
(6) The reception complete interrupt request signal (INTCBnR) is output.
(7) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to
To continue transfer, repeat steps (5) and (6) before (7).
Preliminary User’s Manual U17566EE1V2UM00
time as specifying the transfer mode using the CBnDIR bit, to set the
reception enabled status.
stop the operation of CSIBn (end of reception).
Read the CBnRX register.
0
1
0
1
0
1
0
(6)
1
55H
1
0
55H
1
Clocked Serial Interface (CSIB)
0
1
0
1
(6)
0
AAH
AAH
(7)
00H
00H