upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 588

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 18
588
Condition for clearing (CLDn = 0)
• When the SCLn pin is at low level
• When the IICEn = 0 (operation stop)
• After reset
Condition for clearing (DADn = 0)
• When the SDAn pin is at low level
• When the IICEn = 0 (operation stop)
• After reset
The digital filter can be used only in fast-speed mode.
In fast-speed mode, the transfer clock does not vary regardless of the DFCn bit setting (on/off).
The digital filter is used to eliminate noise in fast-speed mode.
SMCn
CLDn
DADn
DFCn
0
1
0
1
0
1
0
1
Initial Value
Address
The SCLn pin was detected at low level.
The SCLn pin was detected at high level.
The SDAn pin was detected at low level.
The SDAn pin was detected at high level.
Operation in standard mode.
Operation in fast-speed mode.
Digital filter off.
Digital filter on.
Access
(4)
IICCLn - IICn clock select registers
The IICCLn registers set the transfer clock for the I
The SMCn, CLn1, and CLn0 bits are set by the combination of the IICXn.CLXn
bit and the OCKSTHn, OCKSn[1:0] bits of the OCKSn register (see “Transfer
rate setting“ on page 590).
This register can be read/written in 8-bit or 1-bit units.
CLDn and DADn bits are read-only.
<base> + 4
00
Preliminary User’s Manual U17566EE1V2UM00
H
R/W
. This register is cleared by any reset.
Detection of SCLn pin level (valid only when IICCn.IICEn = 1)
7
0
Detection of SDAn pin level (valid only when IICEn = 1)
H
R/W
6
0
Digital filter operation control
Operation mode switching
CLDn
R
5
Condition for setting (CLDn = 1)
• When the SCLn pin is at high level
Condition for setting (DAD0n = 1)
• When the SDAn pin is at high level
DADn
R
4
SMCn
R/W
3
2
DFCn
Cn bus.
R/W
2
CLn1
R/W
1
I
2
C Bus (IIC)
CLn0
R/W
0