upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 324
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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Chapter 8
324
Figure 8-1
Table 8-2
8.5 Transfer Type
8.6 Transfer Object
Buffer register configuration
All DMA transfers of this microcontroller are two-cycle transfers.
In two-cycle transfer, data transfer is performed in two cycles: a read cycle
(source to DMAC) and a write cycle (DMAC to destination).
In the first cycle, the source address is output and reading is performed from
the source to the DMAC. In the second cycle, the transfer destination address
is output and writing is performed from the DMAC to the transfer destination.
The following transfer objects can be specified as source and destination:
Transfer objects
Preliminary User’s Manual U17566EE1V2UM00
Source \
Destination
Data read
Data write
Internal RAM
Peripherals
register
Master
Internal RAM
–
√
register
Slave
DMA Controller (DMAC)
Peripherals
√
√
controller
Address/
count
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