upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 466

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upd70f3422gj-gae-qs-ax

Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
Chapter 13
466
GCCn1 Master register
GCCn1 Slave register
Figure 13-14
INTTGnCC1
Caution
TM G n0
ENFG0
Note
(3)
(f) When GCCnm (m = 1 to 4) is rewritten during operation (match and
When the value of GCCn1 is changed from 0555H to 0AAAH, the operation
described below is performed.
TMGn0 is selected as the counter, and 0FFFH is set in GCCn0.
Timing when GCCnm is rewritten during operation (match and clear)
To perform successive write access during operation, for rewriting the GCCny
register, you have to wait for minimum 7 peripheral clocks periods (f
PMW output (match and clear)
Basic settings (m = 1 to 4):
The PWM mode is activated by setting the SWFGnm and the CCSGnm bit to
"1".
Preliminary User’s Manual U17566EE1V2UM00
clear)
0555H
SWFGnm
CCSGnm
CCSGn0
CCSGn5
TBGnm
Ma tch
Bit
0555H
Reload in 5 clock periods
0AAAH
Value
1
1
Note
Note
X
1
1
16-bit Multi-Purpose Timer G (TMG)
Remark
match and clear mode
enable TOGnm
Compare mode for
GCCnm
assign counter
for GCCnm
0: TMGn0
1: TMGn1
Ma tch
0AAAH
SPCLK0
).

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