TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 94

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TMP93xy20FG

Manufacturer Part Number
TMP93xy20FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP93xy20FG

Package
LQFP144
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
M/P
Rom Combinations
64
Ram Combinations
2
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
-
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
4
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
-
Dual Clock
Y
Number Of I/o Ports
88
Power Supply Voltage(v)
4.5 to 5.5
4.
5.
Comparator
register is set. When they match, the up counter is cleared to 0 and an interrupt signal
(INTT0, INTT1, INTT2, and INTT3) is generated. If the timer flip-flop inversion is enabled,
the timer flip-flop is inverted at the same time.
Timer flip-flop
(8-bit comparator output).
<TFF1IE>.
TFFCR<TFF3C1:0> <TFF1C1:0> sets 0 or 1 to TFF1 and TFF3. Additionally, writing 00 to
this bit inverts the value of TFF1 and TFF3 (Software inversion).
pin (also used as P83). When using the TFF1 and TFF3 contents as the timer output, the
timer flip-flop should be set by the port 6 and 8 function registers P6FC and P8FC
beforehand.
A comparator compares the value in the up counter with the values to which the timer
The timer flip-flop (TFF1 and TFF3) is a flip-flop inverted by the match detect signal
Inverting is enabled or disabled by the timer flip-flop control register TFFCR<TFF3IE>,
After a reset operation, the value of TFF1 and TFF3 are undefined. Writing 01 or 10 to
The values in TFF1 and TFF3 can be output to the TO1 pin (also used as P67) and TO3
93CS20-92
TMP93CS20
2004-02-10

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