TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 135

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

TREG8-WR
T16CR
TREG8
TREG9
T16CR
T8FFCR
T8MOD
P7CR
P7FC
TRUN
T16CR
T16CR<DB8EN>
Figure 3.8.21 shows the block diagram of this mode.
TI8
φT1
φT4
φT16
Selector
← − X − 0 − 0 − −
← *
← *
← − X − 0 − 1 − −
← X X 0 0 1 1 1 0
← 0 0 1 0 0 1 *
← − − − − − 1 − −
← − − X X X 1 X X
← 1 X − − − − − −
← − X − 1 − 1 − −
X: Don’t care, −: No change
7 6 5 4 3 2 1 0
*
*
Figure 3.8.21 Block Diagram of 16-Bit PPG Mode
Selector
*
*
*
*
*
*
*
*
16-bit comparator
Register buffer 8
(** = 01, 10, 11)
*
*
*
*
TREG8
*
*
*
*
*
*
*
*
*
*
*
*
93CS20-133
Internal data bus
*
*
*
*
*
up counter
16-bit
UC8
Match
Disable double buffer of TREG8.
Stop timer 8.
Set the duty (16 bits).
Set the cycle (16 bits).
Enable double buffer of TREG8.
(Change the duty and cycle at the interrupt INTTR9.)
Set the mode to invert TFF8 at the match with TREG8 or
TREG9, and also set TFF8 to 0.
Select the internal clock for the input, and disable the capture
function.
Assign P72 as TO8.
Start prescaler.
Start timer 8.
16-bit comparator
TREG9
Clear
T16CR<T8RUN>
TO8 (PPG output)
Flip-flop
(TFF8)
Match
TMP93CS20
2004-02-10