TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 25

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

Interrupt Receiving Status
♦:
○:
×:
−:
*1:
Note: When release of the HALT mode is executed by an INT0 interrupt of the level mode in the interrupt
Example of releasing the RUN mode:
HALT mode
After release of the HALT mode, the CPU starts interrupt processing. (RESET initializes LSI.)
After release of the HALT mode, the CPU starts executing the next instruction that follows the HALT
instruction.
Cannot be used to release the HALT mode.
This combination type does not exist because the priority level (Interrupt request level) of
non-maskable interrupts is fixed to the highest priority level 7.
Release the HALT mode is executed after the warm-up cycle is completed.
enabled status, maintain level “H” until the start of interrupt processing. If level “L” is set before the
start of interrupt processing, interrupt processing is correctly started.
An INT0 interrupt releases the halt state when the RUN mode is on.
NMI
INTWDT
INT0 to 4, INTKEY
INTRTC
INT7 to B
INTT0 to 3
INTTR4 to B
INTTO4, 6, 8, A
INTRX0, TX0
INTRX1, TX1
INTS2
INTAD
RESET
Address
8203H
8206H
8209H
820BH
820EH
820FH
INT0
Table 3.3.6 Halt Release Sources and Halt Release Operations
resetting time (3ms or more) for the operation of the oscillator to stabilize.
the state it was in before the HALT instruction was executed.
due to interrupts maintains all setting contents in their states before the HALT
instruction was executed.)
When the HALT mode is released by resetting, the internal RAM data maintains
However the other setting contents are initialized. (Release of the HALT mode
LD
LD
EI
LD
HALT
LD
(Interrupt level) ≥ (Interrupt mask)
RUN
(IIMC), 00H
(INTE0AD), 06H
5
(WDMOD), 00H
XX, XX
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
Interrupt Enabled
IDLE2
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
×
×
93CS20-23
IDLE1
♦
♦
♦
♦
×
×
×
×
×
×
×
×
×
;
;
;
;
;
Selects interrupt rising edge for INT0.
Sets interrupt level to 6 for INT0.
Sets interrupt level to 5 for CPU.
Sets HALT mode to run.
Halts CPU.
STOP
♦
×
×
×
×
×
×
×
×
×
×
♦
♦
* 1
* 1
(Interrupt level) < (Interrupt mask)
RUN
○
○
♦
−
−
×
×
×
×
×
×
×
×
Interrupt Disabled
IDLE2
INT0 interrupt
○
○
♦
−
−
×
×
×
×
×
×
×
×
RETI
IDLE1
○
○
♦
−
−
×
×
×
×
×
×
×
×
TMP93CS20
2004-02-10
STOP
♦
−
−
○
×
×
×
×
×
×
×
×
×
* 1