TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 32

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

3.4
Interrupts
interrupt controller.
levels of priority can also be assigned to each maskable interrupt. Non-maskable interrupts
have a fixed priority of 7.
interrupt source to the CPU. When more than one interrupt is generated simultaneously, the
interrupt controller sends the value of the highest priority (7 for non-maskable interrupts is the
highest) to the CPU.
register (IFF2 to IFF0). If the value sent is greater than in that the CPU interrupt mask
register, the interrupt is accepted. However, software interrupts and illegal instruction
execution interrupts are not compared with the <IFF2:0> register. They are given top priority.
The value in the CPU interrupt mask register (IFF2 to IFF0) can be changed using the EI
instruction. Executing EI n changes the contents of <IFF2:0> to n. For example, programming
EI 3 enables acceptance of maskable interrupts with a priority of 3 or greater, and
non-maskable interrupts which are set in the interrupt controller. When EI or EI 0 is
programmed, maskable interrupts with a priority of 1 or greater, and non-maskable interrupts
are enabled in the interrupt instructions. (In the same way as the EI 1)
Since the priority values for maskable interrupts are 0 to 6, the DI instruction is used to disable
acceptance of maskable interrupts. The EI instruction becomes effective immediately after
execution. (with the TLCS-90, the EI instruction becomes effective after execution of the next
following instruction.)
micro DMA processing mode. Micro DMA is a mode used by the CPU to automatically transfer
byte or word data. It enables the CPU to process interrupts such as data saves to built-in I/Os at
high speed.
Interrupts are controlled by the CPU interrupt mask register SR<IFF2:0> and the built-in
Altogether the TMP93CS20 has the following 45 interrupt sources:
A fixed individual interrupt vector number is assigned to each interrupt source; any one of 6
When an interrupt is generated, the interrupt controller sends the value of the priority of the
The CPU compares the value of the priority sent, with the value in the CPU interrupt mask
The DI instruction operates in the same way as the EI 7 instruction, setting <IFF2:0> = 7.
In addition to the general-purpose interrupt processing mode described above, there is also a
Figure 3.4.1 is a flowchart showing overall interrupt processing.
•
•
•
Interrupts from the CPU, 9 sources
(Software interrupts, and illegal (Undefined) instruction execution)
Interrupts from external pins (
wakeup), 12 sources
Interrupts from built-in I/Os, 24 sources
93CS20-30
NMI
, INT0 to INT4, INT7 to INTB, and key-on
TMP93CS20
2004-02-10