TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 159

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

(3) Serial clock generation circuit
(4) Receiving counter
(5) Receiving control
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according to the SIOCLK clock. 16 pulses of SIOCLK are used for receiving 1 bit of data,
and the data bit is sampled three times at the 7th, 8th, and 9th clock.
respectively, the received data is evaluated as 1. The sampled data 0, 0, and 1 is
evaluated such that the received data bit is determined to be 0.
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This circuit generates the basic clock for transmitting and receiving data.
The receiving counter is a 4-bit binary counter used in UART mode and counts up
With these three samples, the received data bit is evaluated by the majority rule.
For example, if the sampled data bit is 1, 0, and 1 at 7th, 8th, and 9th clock
I/O interface mode
UART mode
I/O interface mode
UART mode
will be generated by dividing the output of the baud rate generator by 2 as
described before. When in SCLK input mode with the setting of SC0CR<IOC> = 1,
the rising edge or falling edge will be detected according to the setting of the
SC0CR<SCLKS> register to generate the basic clock.
clock, internal clock φ1 (Max 625 kbps at fc = 20 MHz), or the match detect signal
from timer 0 or the external clock (Channel 0) to generate the basic clock SIOCLK.
signal will be sampled at the rising edge of the shift clock which is output to the
SCLK0 pin.
will be sampled at the rising edge or falling edge of the SCLK0 input according to
the setting of the SC0CR<SCLKS> register.
majority. When two or more 0 are detected during the 3 samples, it is recognized as
start bit and the receiving operation is started.
When in SCLK output mode with the setting of SC0CR<IOC> = 0, the basic clock
The setting of SC0MOD<SC1:0> will select between the baud rate generator
When in SCLK output mode with the setting of SC0CR<IOC> = 0, the RXD0
When in SCLK input mode with the setting SC0CR<IOC> = 1, the RXD0 signal
The receiving control block has a circuit for detecting the start bit by the rule of
The data being received is also evaluated by the majority rule.
93CS20-157
TMP93CS20
2004-02-10