TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 43

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TMP93xy20FG

Manufacturer Part Number
TMP93xy20FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP93xy20FG

Package
LQFP144
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
M/P
Rom Combinations
64
Ram Combinations
2
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
-
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
4
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
-
Dual Clock
Y
Number Of I/o Ports
88
Power Supply Voltage(v)
4.5 to 5.5
0
0
0
0
1
1
Note 1: n: Corresponds to micro DMA channels 0 to 3.
Note 2: Execution time: When setting source address/destination address area to 16-bit bus, 0 waits.
Note 3: Do not use any codes for transfer mode registers other than those indicated above.
0
0
0
1
1
0
0
(3) Transfer mode register details
0
1
0
1
0
1
0
Z Transfer destination address INC mode....................... for I/O to memory
Z Transfer destination address DEC mode...................... for I/O to memory
Z Transfer source address INC mode ............................. for memory to I/O
Z Transfer source address DEC mode ............................ for memory to I/O
Z Fixed address mode ................................................................. I/O to I/O
1 Counter mode ........................................................... for interrupt counter
DMADn+/DMASn+: Post-increment (Increments register value after transfer).
DMADn−/DMASn−: Post-decrement (Decrements register value after transfer).
0
Z: 0 = Byte transfer, 1 = Word transfer
(DMADn+) ← (DMASn)
DMACn ← DMACn − 1
if DMACn = 0 then INT.
(DMADn−) ← (DMASn)
DMACn ← DMACn − 1
if DMACn = 0 then INT.
(DMADn) ← (DMASn+)
DMACn ← DMACn − 1
if DMACn = 0 then INT.
(DMADn) ← (DMASn−)
DMACn ← DMACn − 1
if DMACn = 0 then INT.
(DMADn) ← (DMASn)
DMACn ← DMACn − 1
if DMACn = 0 then INT.
DMASn ← DMASn + 1
DMACn ← DMACn − 1
if DMACn = 0 then INT.
0
Mode
Note: When setting values for this register, set the upper 4 bits to 0.
93CS20-41
Execution time
16 states
16 states
16 states
16 states
16 states
11 states
(1.6 µs)
(1.6 µs)
(1.6 µs)
(1.6 µs)
(1.6 µs)
(1.1 µs)
TMP93CS20
2004-02-10

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