TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 44

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

3.4.3
Interrupt Controller
shows the interrupt controller; the right half includes the CPU interrupt request signal
circuit and the halt release signal circuit.
request flag, interrupt priority setting register, and a register for storing the micro DMA
start vector.
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INTE0AD as follows.
This also allows the interrupt to be identified by the software.
register (e.g., INTE0AD or INTE43) provided for each interrupt source. Interrupt priority
levels to be set range from or 1 to 6. Except for NMIs (Non-maskable interrupts), writing 0
or 7 as the interrupt priority disables the corresponding interrupt request. The priority of
non-maskable interrupt sources (
requests with the same interrupt level are generated simultaneously, interrupts are
accepted in accordance with the default ranking of priorities.
simultaneous interrupts, and sends it and its vector address to the CPU. The CPU
compares the priority value <IFF2:0> set in the status register, with the priority value sent
by the interrupt request signal; if the latter is higher, the interrupt is accepted. Then the
CPU sets in CPU SR<IFF2:0> a value equal to one plus the priority value of the interrupt
request just received. Interrupt requests whose priority values equal or are higher than the
value set in the register are accepted concurrently with execution of the previous interrupt
routine. When interrupt processing is completed (after execution of the RETI instruction),
the CPU restores to CPU SR<IFF2:0> the priority value saved in the stack before the
interrupt was generated.
Unlike other micro DMA registers (DMAS, DMAD, DMAM, and DMAC), these are I/O
registers. Writing the start vector of the interrupt source for micro DMA processing (See
Table 3.4.1), enables the corresponding interrupt to be processed by micro DMA. Please
note that appropriate values must be set in the micro DMA parameter registers (e.g.,
DMAS and DMAD) prior to the beginning of micro DMA processing.
Figure 3.4.4 is a block diagram of the interrupt circuits. The left half of the diagram
Each interrupt channel (Total of 36 channels) in the interrupt controller has an interrupt
The flag is cleared to 0 when any of the following conditions are met.
For example, to clear the INT0 interrupt request, after the DI instruction set the register
The status of the interrupt request flag is detected by reading the corresponding clear bit.
The interrupt priority can be set by writing the priority in the interrupt priority setting
The interrupt controller selects the interrupt request with the highest priority among the
The interrupt controller also has four registers used to store the micro DMA start vector.
upon resetting
when the CPU reads the interrupt vector after acceptance of an interrupt
when the CPU executes an instruction that clears the interrupt from that channel
(Writes 0 in <IxxC> of the interrupt priority setting register)
LD
(INTE0AD), − − − − 0 − − − B
93CS20-42
NMI
pin, watchdog timer, etc.) is fixed to 7. If interrupt
TMP93CS20
2004-02-10