TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 243

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

Symbol
TRUN
TREG0
TREG1
T10MOD
TFFCR
TREG2
TREG3
T32MOD
TRDC
(6) Timer control (1/5)
Timer
control
8-bit
timer
register 0
8-bit
timer
register 1
8-bit
timer 0,1
source
CLK and
mode
8-bit
timer
flip flop
control
8-bit
timer
register 2
8-bit
timer
register 3
8-bit
timer 2,3
source
CLK and
mode
Timer
register
double
buffer
control
register
Name
Address
(Prohibit
(Prohibit
(Prohibit
(Prohibit
RMW)
RMW)
RMW)
RMW)
20H
22H
23H
24H
25H
26H
27H
28H
29H
00: 8-bit timer
01: 16-bit timer
10: 8-bit PPG
11: 8-bit PWM
00: Invert TFF3
01: Set TFF3
10: Clear TFF3
11: Don’t care
00: 8-bit timer
01: 16-bit timer
10: 8-bit PPG
11: 8-bit PWM
PRRUN
TFF3C1
T01M1
T23M1
R/W
7
0
0
1
0
W
TFF3C0
T01M0
T23M0
6
0
1
0
93CS20-241
1: TFF3
00: −
01: 2
10: 2
11: 2
00: −
01: 2
10: 2
11: 2
PWM01
PWM21
T6RUN
TFF3IE
invert
enable
5
0
0
0
0
6
7
8
6
7
8
Prescaler and timer run/stop control
− 1PWM
− 1
− 1
− 1 PWM
− 1
− 1
R/W
0: Stop and clear
1: Run (Count up)
1: Timer 3
PWM00
PWM20
T4RUN
TFF3IS
invert
enable
4
0
0
0
0
Undefined
Undefined
Undefined
Undefined
R/W
R/W
W
W
W
W
−
−
−
−
00: TO0TRG
01: φT1
10: φT16
11: φT256
00: TO2TRG
01: φT1
10: φT16
11: φT256
T1CLK1
TFF1C1
T3CLK1
00: Invert TFF1
01: Set TFF1
10: Clear TFF1
11: Don’t care
T3RUN
3
0
0
1
0
R/W
W
T1CLK0
TFF1C0
T3CLK0
T2RUN
2
0
0
1
0
1: TFF1
0: Double
1: Double
00: TI0 Input
01: φT1
10: φT4
11: φT16
00: TI2 input
01: φT1
10: φT4
11: φT16
T0CLK1
T2CLK1
TR2DE
T1RUN
TFF1IE
invert
enable
buffer
disable
buffer
enable
1
0
0
0
0
TMP93CS20
0
2004-02-10
R/W
R/W
1: Timer 1
0: Double
1: Double
T0CLK0
T2CLK0
TR0DE
T0RUN
TFF1IS
invert
enable
buffer
disable
buffer
enable
0
0
0
0
0
0