TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 167

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

(2) Mode 1 (7-bit UART mode)
Setting example:
(3) Mode 2 (8-bit UART mode)
Setting example:
P6CR
P6FC
SC0MOD
SC0CR
BR0CR
TRUN
INTES0
SC0BUF
to 01.
enabled or disabled by serial channel control register SC0CR<PE>, and even parity or
odd parity is selected by SC0CR<EVEN> when <PE> is set to 1 (Enable).
mode, the parity bit can be added (the addition of a parity bit is enabled or disabled by
SC0CR<PE>) and even parity or odd parity is selected by SC0CR<EVEN> when <PE>
is set to 1 (Enable).
The 7-bit mode can be set by setting serial channel mode register SC0MOD<SM1:0>
In this mode, a parity bit can be added, and the addition of the parity bit can be
The 8-bit UART mode can be specified by setting SC0MOD<SM1:0> to 10. In this
← − − − − 1 − − −
← − − − X 1 − − −
← X 0 − X 0 1 0 1
← X 1 1 X X X 0 0
← 0 0 1 0 0 1 0 1
← 1 X − − − − − −
← 1 1 0 0 − − − −
← *
X: Don’t care, −: No change
7 6 5 4 3 2 1 0
Start
* Clock condition
* Clock condition
When transmitting data with the following format, the control registers should be set as described
below. Channel 0 is explained here.
When receiving data with the following format, the control register should be set as described
below.
*
Start
*
Bit0
*
Bit0
Direction of transmission (Transmission rate: 9600 bps at fc = 12.288 MHz)
*
1
*
Direction of transmission (Transmission rate: 2400 bps at fc = 12.288 MHz)
1
*
93CS20-165
2
*
2
System clock:
Clock gear:
Prescaler clock: System clock
System clock:
Clock gear:
Prescaler clock: System clock
3
3
4
Select P63 as the TXD0 pin.
Set 7-bit UART mode.
Add even parity.
Set transfer rate at 2400 bps.
Start the prescaler for the baud rate generator.
Enable INTTX0 interrupt and set interrupt level 4.
Set data for transmission.
4
5
High frequency (fc)
1 (fc)
High frequency (fc)
1 (fc)
5
6
6
7
parity
Even
parity
Odd
Stop
Stop
TMP93CS20
2004-02-10