TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 179

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

SCL line
SDA line
Start condition
(6) Transmitter/receiver selection
(7) Start/stop condition generation
Figure 3.10.9 Start Condition Generation and Slave Address Generation
Master mode
Slave mode
Mode
<TRX> to 0 for operation as a receiver. When data with an addressing format is
transferred in the slave mode, when a slave address with the same value that an
I2CAR or the GENERAL CALL is received (All 8-bit data are 0 after the start
condition), <TRX> is set to 1 by the hardware if the direction bit (R/W) sent from
the master device is 1, and is set to 0 by the hardware if the bit is 0. In the master
mode, after the acknowledge signal is returned from the slave device, <TRX> is
set to 0 by the hardware if a transmitted direction bit is 1, and set to 1 by the
hardware if it is 0. When the acknowledge signal is not returned, the current
condition is maintained.
detected or arbitration is lost.
changing.
the direction bit are not recognized. They are handled as data just after
generating a start condition. The TRX was not changed by the hardware.
are output by writing 1 to SBICR2<MST, TRX, BB, PIN>. It is necessary to set 1
to SBICR1<ACK> beforehand.
writing 1 to <MST, TRX, PIN> and 0 to <BB>. Do not modify the contents of <MST,
TRX, BB, PIN> until the stop condition is generated on a bus.
level by another device, a stop condition is generated after releasing the SCL line.
to 1 when the start condition on a bus is detected, and is set to 0 when the stop
condition is detected.
Set SBICR2<TRX> to 1 for operating the TMP93CS20 as a transmitter. Set
<TRX> is cleared to 0 by the hardware after the stop condition on the I
The following shows <TRX> change conditions in each mode and <TRX> after
When the TMP93CS20 operates in the free data format, the slave address and
When SBISR<BB> is 0, the start condition and slave address and direction bit
When SBISR<BB> is 1, a sequence of generating the stop condition is started by
When a stop condition is generated and the SCL line on the bus is set to low
The bus condition can be indicated by reading the contents of <BB>. <BB> is set
SCL line
SDA line
A6
1
Direction Bit
Figure 3.10.10 Stop Condition Generation
0
1
0
1
A5
2
Slave address and the direction bit
A4
A received slave address is the
same as a value set to I2CAR.
ACK signal is returned.
93CS20-177
3
Change Condition
A3
4
Stop condition
A2
5
A1
6
<TRX> After
Changing
A0
7
0
1
1
0
R/
8
W
Acknowledge signal
TMP93CS20
2004-02-10
9
2
C bus is