TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 217

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

3.14.3
LCD Display
(1) Setting of display data
(2) Blanking
area between addresses 000080H to 000093H.
and transferred to the LCD driver. The LCD driver generates a segment signal and a
common signal according to the display data and the driving method. The display
pattern can be changed by changing data stored in the display data area in the
program.
on when a display data is 1. They turn off when a display data is 0.
the LCD driving methods.
output to the COM and SEG pins, and the LCD turns off.
Note: Although a pin output only for segments (SEG0 to SEG23), common output, and
Driving Method
DBR0A
DBR0B
DBR0C
DBR0D
DBR0E
DBR0F
DBR00
DBR01
DBR02
DBR03
DBR04
DBR05
DBR06
DBR07
DBR08
DBR09
DBR10
DBR11
DBR12
DBR13
A display data is stored in a display data area which is allocated in 20 bytes address
The display data stored in the display data area is automatically read by hardware,
Figure 3.14.6 shows SEG and COM pins in the display data areas. These pins turn
In addition to a number of pixels, a number of bits in the display data area depend on
When the CHPCR<EDSP> is cleared to 0, a blanking occurs. The GND level is
1/4 duty
1/3 duty
1/2 duty
Address
Static
−: Bits not to be used in the display data area
Table 3.14.4 A Number of Bits in the Display Data Area
output port/segment combination pin (P9 port) output serves as GND level at the
time of reset, an output port/segment combination pin (PA port) will benefit an
open-drain output in a high impedance state. Therefore, when port A is used as a
segment and the reset input from the exterior becomes remarkably long, there is a
possibility of doing the influence to which the display of LCD spreads etc.
008AH
008BH
008CH
008DH
008EH
008FH
0080H
0081H
0082H
0083H
0084H
0085H
0086H
0087H
0088H
0089H
0090H
0091H
0092H
0093H
Figure 3.14.6 LCD Display Data Area
SEG0 to SEG39 can be read and written.
COM3
Bit7
Bit 7/3
COM3
−
−
−
COM2 COM1
Bit6
93CS20-215
SEG11
SEG13
SEG15
SEG17
SEG19
SEG21
SEG23
SEG25
SEG27
SEG29
SEG31
SEG33
SEG35
SEG37
SEG39
SEG1
SEG3
SEG5
SEG7
SEG9
Bit5
Bit 6/2
COM2
COM2
−
−
COM0
Bit4
COM3
Bit3
Bit 5/1
COM1
COM1
COM1
−
COM2
Bit2
SEG10
SEG12
SEG14
SEG16
SEG18
SEG20
SEG22
SEG24
SEG26
SEG28
SEG30
SEG32
SEG34
SEG36
SEG38
SEG0
SEG2
SEG4
SEG6
SEG8
COM1
Bit1
Bit 4/0
COM0
COM0
COM0
COM0
COM0
Bit0
ビ
TMP93CS20
2004-02-10