TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 123

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

TREG4-WR
T16CR
TRUN
TREG4
TREG5
T16CR
T4FFCR
T4MOD
P4CR
P4FC
TRUN
T16CR<DB4EN>
TI4
φT1
φT4
φT16
Selector
Figure 3.8.12 shows the block diagram of this mode.
← 0 X X X − − − 0
← − X − 0 − − − −
← *
← *
← 0 X X X − − − 1
← X X 0 0 1 1 1 0
← 0 0 1 0 0 1 *
← − − − − − − 1 −
← X X X X − X 1 X
← 1 X − 1 − − − −
X: Don’t care, −: No change
7 6 5 4 3 2 1 0
*
*
Figure 3.8.12 Block Diagram of 16-Bit PPG Mode
*
*
*
*
Selector
*
*
*
*
16-bit comparator
Register buffer 4
(** = 01, 10, 11)
*
*
*
*
TREG4
*
*
*
*
*
*
*
*
*
*
*
*
16-bit up counter
93CS20-121
Internal data bus
*
*
*
*
*
UC4
Match
Disable double buffer of TREG4.
Stop timer 4.
Set the duty (16 bits).
Set the cycle (16 bits).
Enable double buffer of TREG4.
(Change the duty and cycle at the interrupt INTTR5.)
Set the mode to invert TFF4 at the match with TREG4 or
TREG5, and also set TFF4 to 0.
Select the internal clock for the input, and disable the capture
function.
Assign P41 as TO4.
Start timer 4.
16-bit comparator
TREG5
Clear
TRUN<T4RUN>
TO4 (PPG output)
Flip-flop
(TFF4)
Match
TMP93CS20
2004-02-10