TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 145

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

SC0CR
(0051H)
Bit symbol
Read/Write
After reset
Function
Note 1: To use baud rate generator, set TRUN<PRRUN> to 1, putting the prescaler in RUN mode.
Note 2: As all error flags are cleared after reading, do not test only a single bit with a bit-testing instruction.
Received
data bit8
Undefined
RB8
7
R
Figure 3.9.3 Serial Control Register (Channel 0, SC0CR)
0: Odd
1: Even
Parity
EVEN
6
0
R/W
0: Disable
1: Enable
Parity
addition
PE
5
0
93CS20-143
Overrun
OERR
4
0
R (Cleared to 0 when read)
1: Error
Parity
PERR
Select I/O interface input clock
Edge selection for SCLK pin (Input mode only)
Framing error flag
Parity error flag
Overrun error flag
Enable parity addition
Received data bit8
8-bit UART mode
(Parity)
9-bit UART mode
Addition/check of even parity
3
0
0
1
0
1
0
1
0
1
Baud rate generater (Note 1)
SCLK0 pin input
Transmits and receives
data at rise edge of SCLK0
Transmits and receives
data at fall edge of SCLK0
Disable
Enable
Odd parity
Even parity
Framing
FERR
2
0
Stores received parity bit
Stores received data bit8
0: SCLK0
1: SCLK0
SCLKS
Cleared to 0
when read.
1
0
TMP93CS20
R/W
2004-02-10
0: Baud rate
1: SCLK0
generator
pin input
IOC
0
0