TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 186

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

SCL (Bus)
SCL pin
SDA pin
<LRB>
<BB>
<PIN>
(4) Stop condition generation
(5) Restart
1 to SBICR2<MST, TRX, PIN>, and 0 to <BB>. Do not modify the contents of <MST,
TRX, BB, PIN> until the stop condition is generated on the bus. When SBICR2<MST,
TRX, PIN> are written “1” and <BB> is written “0” (generate stop condition in master
mode), <BB> changes to “0” by internal SCL changes to “1”, without waiting stop
condition. To check whether SCL and SDA pin are “1” by sensing their ports is needed to
detect bus free condition.
slave device during transferring data. The following explains how to restart the
TMP93CS20.
the high level and the SCL pin is released. Since a stop condition is not generated on the
bus, the bus is assumed to be in a busy state from other devices. And confirm SCL pin,
that SCL pin is released and become bus-free state by SBISR<BB> = “0” or signal level
“1” of SCL pin in port mode. Test the <LRB> until it becomes 1 to check that the SCL
line of the bus is not set to low level by other devices. After confirming that the bus stays
in a free state, generate a start condition with procedure (2).
software from the time of restarting to confirm that the bus is free until the time to
generate the start condition.
When SBISR<BB> is 1, a sequence of generating a stop condition is started by writing
Restart is used to change the direction of data transfer between a master device and a
Clear 0 to the <MST>, <TRX>, and <BB> and set 1 to the <PIN>. The SDA pin retains
In order to meet setup time when restarting, take at least 4.7 µs of waiting time by
Figure 3.10.17 Timing Diagram when Restarting the TMP93CS20
“0” → <MST>
“0” → <TRX>
“0” → <BB>
“1” → <PIN>
9
“1” → <MST>
“1” → <TRX>
“0” → <BB>
“1” → <PIN>
Internal SCL
SCL pin
SDA pin
<PIN>
<BB> (Read)
Figure 3.10.16 Stop Condition Generation
93CS20-184
“1” → <MST>
“1” → <TRX>
“1” → <BB>
“1” → <PIN>
4.7 µs (Min)
Stop condition
Start condition
TMP93CS20
2004-02-10